Abstract:
The demand for FPGA-based processor cores increases as more embedded systems are built on FPGA platforms. The flexible choice is the "soft" processor IP core, a processor implemented in the reconfigurable logic of the FPGA. Commercial and academic soft processors have been widely deployed, but most are synthesized implementations of legacy instruction sets that fill up large and costly FPGAs. With high performance media processing applications dominating the embedded scene, and many modern microprocessors adopting the SIMD technology, it is a fact that soft cores could also make use of array and vector processing functionality. This thesis presents the SIxD, a configurable CPU soft core designed to combine computer architecture basics to exploit instruction level parallelism with the flexibility and customizability advantages of soft cores realized on reconfigurable fabric. With run-time configuration options such as variable data space, customizable instruction set, and array processing capabilities, the SIxD is a novel soft core that can be configured to fit in as low as a forty thousand system gate FPGA, or offer higher performance array processing on bigger FPGAs.
