Equivalence checking of designs modeled in simulink implemented in low level

Abstract

We propose methodologies for checking the equivalence of analog and digital Simulink models and their low level implementations. For digital methodology, we develop a flow utilizing commonly used tools used in digital integrated circuit design. Digital model can be designed by built-in Simulink libraries or user-defined functions. These models are converted to register-transfer level (RTL) implementations by us age of either Matlab’s HDL Coder tool or Real Time Workshop followed by Catapult. Manual RTL implementation is compared to the converted RTL via Formality tool to decide equivalence. For the analog methodology, equivalence is decided by comparing predetermined performance parameters from simulations of model and the circuit level implementation. Simulations are done for different input parameters, which charac terize the design. By means of this, a space of input parameters is found, where the model and the circuit level implementation are equivalent. For the analog methodol ogy, we utilize Matlab’s optimizer firstly, then we develop an evolutionary computation approach, which is a modified version of SPEA2 algorithm. We utilize Quasi Monte Carlo method to generate the samples, which are the input parameter set. This makes it possible to reach the result with less samples. Finally, we integrate process variation analysis to the equivalence checking methodology. To the best of our knowledge, the methodologies we propose for both digital and analog models are the first for check ing equivalence for Simulink. Also the analog equivalence checking methodology with evolutionary computation can be applied to non-Simulink models. We validate digital methodology on designs distributed with Matlab package and Advanced Encryption Standard (AES). Proposed analog methodologies and process variation analysis are validated on inverter, operational amplifier and buck converter.