Abstract:
Digital Signal Processing (DSP) is the most studied area in design automation, because it is one of the most well-established branches of electrical engineering for several years. In the last few years, it is stimulated by the progression of multirate techniques. The key property of multirate algorithms is their computational efficiency. In this thesis, a silicon compiler is developed to reduce design time for the hardware realization of FIR-based multirate DSP algorithms. This is a brand new study, because there does not exist a silicon compiler of this type according to our knowledge. Although multirate algorithms contain decimators and interpolators changing the effective sample rate, the design of synchronous systems using a single-clock signal is possible by this newly developed tool. The designer can achieve this by folding nodes of similar type into a single node. Additionally, the FIR filters followed by a decimator or following an interpolator can be entered as a single node while defining a system at the input of the tool. Also multiplications with the tap coefficients in FIR-based nodes in a fold are handled at the same time to exploit common terms so as to realize those multiplications without multipliers. As a result, the tool produces very efficient layouts in terms of area, power and clock signals. It can also determine the quantization levels of tap coefficients in FIR-based nodes and fractional parts of data bus if the system output error is specified. It also handles module selection under given power, area and delay constraints and scheduling like other well-known silicon compilers. The compiler is programmed to process bit-parallel-digit-serial architectures.
